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交通灯实验报告
- vhdl交通灯实验报告-VHDL traffic lights Experimental Report
mimasuo
- vhdl 实验报告 verilog rs触发器 vhdl实验 vhdl 实验 报告 verilog rs触发器 vhdl实验
数字频率计实验报告
- 课程设计要求设计并用FPGA实现一个数字频率计，具体设计要求如下： 测量频率范围： 10Hz～100KHz 精度： ΔF / F ≤ ±2 % 系统外部时钟： 1024Hz 测量波形： 方波 Vp-p ＝ 3～5 V 硬件设备：Altera Flex10K10 五位数码管 LED发光二极管 编程语言：Verilog HDL / VHDL-curriculum design and FPGA design to achieve a digital frequency meter,
shuzi.rar
- 数字电子钟设计，整点报时，时分秒分模块设计，另附实验报告和实验结果，内容详细不容错过,The design of digital electronic clock, the whole point of time when minutes and seconds sub-module design, an additional test reports and laboratory test results, the details not to be missed
FPQ.rar
- VHDL实现分频器 有仿真图 有实验报告,VHDL simulation of the realization of crossovers have the report there were experimental
CPU
- 一个多周期CPU的完整设计，quartus平台，Verilog实现，内含实验报告，和详细的各模块功能表-Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module
DES_Verilog
- 这是我用Verilog写的DES加解密程序,准确的说这是一份实验报告,里面不但有程序还有简单的注释[主要是针对仿真的波形的],我主要写的是主控部分,密钥生成部分参考了下版原康宏的程序.该程序即可加密也可解密,选用CycloneII器件即能跑到100Mhz以上.-This is what I used to write Verilog the DES encryption and decryption procedures, accurate to say that this is a test
shuzizhong
- 设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。 实验平台： 1. 一台PC机； 2. MAX+PLUSII10.1。 Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, d
CONTROLLER
- NEW！！ 交通灯实验报告 全面-NEW! ! Experimental report provides a comprehensive traffic lights
MyProject
- 3-8译码器的仿真实验。本实验选用的仿真开发软件是MAX+plus II Version 9.3，原理图源文件保存在MyProject目录中，为138decoder.gdf，另有我写的实验报告，呵呵，适合仿真入门-3-8 decoder simulation. Selected in this experiment simulation software is MAX+ Plus II Version 9.3, schematic source files stored in the MyPro
745221frequency
- 用Verilog HDL / VHDL实现的数字频率计（完整实验报告）-Using Verilog HDL/VHDL realization of digital frequency meter (complete test report)
Lift
- VHDL编写的6层电梯控制器，可在Altera的CPLD系统运行实验，内附实验报告-VHDL prepared 6-storey elevator controller in Altera s CPLD system experiment, experimental report containing
reportform
- 数字频率计实验报告,帮助你写一个完美的报告,格式很规范,正品报告模板-it is nice report modole
a
- 8路抢答器 vhdl 实验以及报告-Answer 8 experimental device as well as the report vhdl
bb
- 基于CPLD数字密码锁的设计 实验报告 所有都有 大家参考-CPLD-based design of digital locks all have a test report reference
dianti
- 用verilog写的电梯控制器内附测试文件和实验报告 -Use verilog to write elevator controller with the test documentation and test reports
jiaotongdeng
- 交通灯控制系统的设计和实验报告 8255、8259、8253芯片交通灯-Traffic light control system design and experimental report 8255,8259,8253 chip traffic lights
vhdl
- VHDL实验报告 基于ROM的正弦波发生器的设计-VHDL experiment reports the ROM-based sine wave generator design
vhdl-lab-report
- vhdl实验报告，关于4位选择器，在maxplusII下运行-vhdl lab report
vhdl交通灯
- 实现十字路口两个交通灯的功能，完整实验报告，含源代码(The realization of the intersection of two traffic lights function, complete experimental report, including source code)